China home made DUV machines comes just in time

[retaxis]

Ever Since America put blockade on EUV machines, China went and purchased a large number of DUV machines to stockpile as strategic assets as now America has also banned DUV machines. Those DUV machines wouldn't last forever only 5-10 years and then China would have no more DUV machines to use. Thankfully China is able to now make their own DUV machines and also working to complete their own EUV machine in the next couple of years.

China has started low-volume production of home-grown immersion deep ultraviolet (DUV) lithography machines through state-backed enterprises to bypass Western export restrictions. [1, 2]

Production and Timeline

• • Manufacturer: State-owned Shanghai Aishengna Electronic Technology Group leads the manufacturing effort.
  • Output: China plans to produce about 5 DUV machines this year and roughly 20 machines in 2027.
  • First Deliveries: The initial units are slated for delivery to domestic chipmakers like SMIC, Hua Hong Semiconductor, and CXMT for line validation. [1, 2, 3, 4]

Industry Impact and Comparison

• • Scale: This domestic output remains small compared to industry giant ASML, which ships over 130 DUV systems annually.
  • Technology Gap: The native Chinese DUV machines still trail ASML in performance, reliability, and volume efficiency.
  • Strategic Value: As detailed by Reuters and Tom's Hardware, this step reduces reliance on foreign semiconductor equipment. [1, 2, 3, 4]

 

[retaxis]

The next 10 years in the semiconductor market will be interesting with China making EUV machines functional soon.

AI Overview



China has already built a working prototype of an Extreme Ultraviolet (EUV) lithography machine in a secret Shenzhen lab completed in early 2025, with industry experts and analysts estimating that a fully commercial, production-ready domestic EUV machine could emerge between 2027 and 2030. [1, 2, 3]

Current Status of China's EUV Development

• • Prototype Completion: A state-backed project coordinated with Huawei and built using former ASML engineers finished a working prototype in early 2025. [1, 2]
  • Light Generation: The prototype successfully generates EUV light using an alternative laser-induced discharge plasma (LDP) approach, but it cannot yet mass-produce working functional chips. [1, 2]
  • Production Timeline: While the prototype is currently undergoing testing, scaling it to reliable commercial manufacturing is projected to take until the late 2020s (2028–2030), though some estimates place initial commercial readiness as early as 2027. [1, 2, 3]

 

[retaxis]

In 5-10 years time.

Combining Extreme Ultraviolet (EUV) chips with logic folding results in a super-dense, highly efficient "hyper-3D" semiconductor architecture. [1]
To understand why this combination is so potent, you have to look at the current geopolitical context. In mid-2026, Huawei introduced logic folding under its "Tau Scaling Law" as a creative workaround because US sanctions block Chinese firms from buying ASML's advanced EUV lithography machines. Instead of using EUV to shrink transistors horizontally, logic folding takes standard 7nm-class chips and "folds" the circuitry face-to-face into a dual-layer vertical stack using ultra-fine hybrid bonding. [1, 2, 3, 4, 5]
However, logic folding was never meant to replace EUV permanently; it is an optimization trick born out of restriction. When you actually mix true EUV-fabricated chips with logic folding, you get the best of both worlds. [1]

1. Exponential Transistor Density Boost

• • EUV's Role: Shrinks individual transistors horizontally to fit hundreds of millions into a single square millimeter.
  • Logic Folding's Role: Stacks those already-tiny transistors vertically into multiple active layers.
  • The Result: Instead of the ~53% density jump Huawei gets by folding older 7nm nodes, folding true sub-3nm EUV nodes creates an exponential, multi-fold compounding effect on transistor density. It achieves true next-generation density without waiting for a new lithography node. [1, 2, 3, 4, 5, 6]

2. Solving the "Wire Interconnect" Bottleneck

• • As chips shrink via EUV, the transistors get faster, but the flat, sprawling copper wires connecting them create a massive signal delay (parasitic RC delay). [1, 2]
  • Folding the logic gates face-to-face brings distant circuits right next to each other vertically. [1]
  • This radically shortens internal wiring length by 30% or more, squeezing maximum speed out of EUV chips and pushing clock speeds well past 3GHz to 5GHz. [1, 2, 3]

3. Radical Power Efficiency

• • Shorter wires mean less resistance, less capacitance, and less energy required to push data across the chip.
  • Mixing logic folding with EUV results in a massive dual-reduction in power consumption—saving energy from both the smaller physical transistor geometry (EUV) and the shortened electrical paths (folding). [1, 2, 3]